Application of the Hardware-in-the-Loop Simulation for Updating the Traffic Signal Timing Plans

The objective of this paper is to introduce a concept of applying hardware-in-the-loop simulation for updating traffic signal timing plans. Typically, signal optimization software such as TRANSYT, PASSER among others are utilized to develop signal timing plans. These plans then must be "fine-tuned" to replicate driver behavior as well as the fact that the timing plan is based on mathematics. Presently, the fine-tuning takes place under live traffic conditions, which can lead to unsafe traffic operations, nevertheless is not efficient. In this paper, we introduce the components and configuration of the hardware-in-the-loop simulation and detail recommended procedures and steps to apply hardware-in-the-loop simulation in updating traffic signal timing plans. A diamond interchange in McLean, Virginia, USA is used as a case study to illustrate the procedures. Our analysis on measures of effectiveness (MOEs) from the hardware-in-the-loop simulation indicated proposed timing plan in example case was better than the current plan. We found that hardware-in-the-loop simulation was indeed a great tool in evaluating and fine turning signal timing plans.